general description the max3747/max3747a multirate limiting amplifiers function as data quantizers for oc-3 through oc-48 syn- chronous optical network (sonet), fibre-channel, and gigabit ethernet optical receivers. they are pin-for-pin compatible with the sy88993v from micrel semiconductor, inc. the amplifiers accept a wide range of input voltages and provide constant-level, current- mode logic (cml) output voltages with controlled edge speeds. the max3747 output voltage level is 500mvp-p and the max3747a output voltage is 800mvp-p. the max3747/max3747a limiting amplifiers feature a programmable loss-of-signal detect (los) and an optional disable function (disable). output disable can be used to implement squelch. the max3747/max3747a are available in a 3mm, 10-pin ?ax?package ideal for small form-factor receivers. applications gigabit ethernet sfp/sff optical transceiver modules 1g/2g fibre-channel sfp/sff optical transceiver modules multirate oc-3 to oc-48 fec sfp/sff optical transceiver modules 10g lx4 transceiver modules features ? pin compatible with micrel sy88993v ? 155mbps to 3.2gbps operation ? >57db of gain for the max3747 and max3747a ? <10 - 12 ber with 2mv p-p input amplitude ? 18ma supply current ? chatter-free los with programmable threshold ? output disable function ? pecl-compatible inputs max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers ________________________________________________________________ maxim integrated products 1 ordering information max3745 supply filter v cc max4004 v cc ds1859 3-input diagnostic monitor sfp optical receiver 5-pin to-header host board host filter serdes 50 ? 50 ? max3747 max3747a v ref th gnd los disable in- in+ out- out+ v cc 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 50 ? 50 ? r1 r2 r1 + r2 5k ? v cc_ rx v cc_ host los 4.7k ? to 10k ? t ypical application circuit 19-3297; rev 0; 5/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code max3747 eub -40? to +85? 10 ?ax u10c-4 max3747a eub -40? to +85? 10 ?ax u10c-4 pin configuration appears at end of data sheet. ?ax is a registered trademark of maxim integrated products, inc.
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +2.97v to +3.63v, cml output load is 50 ? to v cc , t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise specified.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) .................................-0.5v to +4.5v voltage at in+, in- ..........................(v cc - 2.4v) to (v cc + 0.5v) voltage at disable, los, th, v ref ..........-0.5v to (v cc + 0.5v) current into los ...................................................-1ma to +9ma current into v ref ..................................................................2ma differential input voltage (in+ - in-) .....................................2.5v continuous current at cml outputs (out+, out-) ..............................................-25ma to +25ma continuous power dissipation (t a = +70 c) 10-pin ?ax (derate 6.9mw/? above +70 c) ...........552mw operating junction temperature range (t j ) .......-55? to +150? storage ambient temperature range (t s ) ...........-55? to +150? parameter symbol conditions min typ max units power supply max3747 includes the cml output current 30 35 max3747a includes the cml output current 36 41 supply current (note 2) i cc max3747/max3747a exclude the cml output current 18 24 ma power-supply noise rejection psnr f < 2mhz 30 db input specification input sensitivity v in-min (note 3) 4 mv p-p input overload v in-max (note 3) 1200 mv p-p output specification output resistance r out 42 50 58 ? differential output return loss dut is powered on, f < 3ghz 15 db max3747a 4mv p-p v in 1200mv p-p 600 800 1000 cml differential output voltage max3747 4mv p-p v in 1200mv p-p 400 500 600 mv p-p differential output signal when disabled ac-coupled outputs, v in-max applied to the input (note 4) 15 mv p-p data-output transition time 20% to 80% (note 4) 70 120 ps transfer characteristic k28.5 pattern at 3.2gbps 13.2 19 prbs 2 23 - 1 equivalent pattern at 2.7gbps (note 6) 14 25 k28.5 pattern at 2.1gbps 12 17 deterministic jitter (notes 4, 5) dj prbs 2 23 - 1 equivalent pattern at 155mbps (note 6) 85 150 ps p-p random jitter v in = 4mv p-p (notes 4, 7) 3.5 5 ps rms input-referred noise v in = 4mv p-p (note 4) 120 150 ? rms low-frequency cutoff 6.4 khz
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +2.97v to +3.63v, cml output load is 50 ? to v cc , t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise specified.) (note 1) parameter symbol conditions min typ max units loss of signal los hysteresis 10log(v deassert / v assert ) (note 4) 1.25 db los-assert/deassert time (notes 4, 8) 2.3 40.0 ? low los assert level v th = -1.3v (notes 4, 9) 2.5 4.1 5.9 mv p-p low los deassert level v th = -1.3v (notes 4, 9) 6.2 9.3 mv p-p medium los assert level v th = -0.68v (notes 4, 9) 22 29 31 mv p-p medium los deassert level v th = -0.68v (notes 4, 9) 44.8 57 mv p-p high los assert level v th = -0.114v (notes 4, 9) 36.0 53.7 63.6 mv p-p high los deassert level v th = -0.114v (notes 4, 9) 86 115 mv p-p ttl/cmos i/o v ref voltage v ref v cc - 1.35 v cc - 1.3v v cc - 1.19 v los output high voltage v oh r los = 4.7k ? to 10k ? to v cc_host (3v) 2.4 v los output low voltage v ol r los = 4.7k ? to 10k ? to v cc_host (3.6v) 0.4 v disable input high v ih 2.0 v disable input low v il 0.8 v disable input current r los = 4.7k ? to 10k ? to v cc_host 10 ? note 1: the data-input transition time is controlled by a 4th-order bessel filter with f -3db = 0.75 x 2.667ghz for all data rates of 2.667gbps and below. the f -3db = 0.75 x 3.2ghz for a data rate of 3.2gbps. note 2: supply current is measured with unterminated outputs or with ac-coupled output termination (see figure 1). note 3: between sensitivity and overload, all ac specifications are met and the output is 0.95 x limited output amplitude. note 4: guaranteed by design and characterization. note 5: the deterministic jitter (dj) caused by the input filter is not included in the dj generation specification. note 6: the prbs 2 23 - 1 equivalent pattern consists of a k28.5 pattern plus 240 ones plus k28.5 pattern plus 240 zeros. note 7: random jitter was measured without using a filter at the input. note 8: the signal at the input is switched between two amplitudes, signal_on and signal_off, as shown in figure 2. note 9: v th is the voltage at pin 5 referenced to v cc (see figure 5).
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers 4 _______________________________________________________________________________________ max3747 max3747a v cc i cc (supply current) i out (cml output current) 50 ? 50 ? figure 1. power-supply current measurement 1db 6db 0v v in time signal on maximum deassert level minimum assert level signal off maximum power-detect window figure 2. los deassert threshold?et 1db below the minimum by receiver sensitivity output eye diagram (minimum input) max3747/max3747a toc01 60mv/div 50ps/div 3.2gbps, 2 23 - 1 prbs, 4mv p-p output eye diagram (maximum input) max3747/max3747a toc02 60mv/div 50ps/div 3.2gbps, 2 23 - 1 prbs, 1200mv p-p t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.)
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers _______________________________________________________________________________________ 5 output eye diagram (minimum input) max3747/max3747a toc03 60mv/div 70ps/div 2.7gbps, 2 23 - 1 prbs, 4mv p-p output eye diagram (maximum input) max3747/max3747a toc04 60mv/div 70ps/div 2.7gbps, 2 23 - 1 prbs, 1200mv p-p output eye diagram at +100 c max3747/max3747a toc05 60mv/div 80ps/div 2.125gbps, cjtpat, 50mv p-p 10 25 20 15 30 35 45 40 50 -40 -20 -10 -30 0 10 20 30 40 50 60 70 80 supply current vs. temperature (excludes output current) max3747/max3747a toc06 temperature ( c) supply current (ma) transfer function (output voltage vs. input voltage) max3747/max3747a toc07 differential input (mv p-p ) differential output (mv p-p ) 4 3 2 1 100 200 300 400 500 600 700 800 900 1000 0 05 max3747a max3747 0 1.5 1.2 0.9 0.6 0.3 1.8 2.1 2.7 2.4 3.0 -40 -20 -10 -30 0 10 20 30 40 50 60 70 80 random jitter vs. temperature max3747/max3747a toc08 temperature ( c) random jitter (ps rms ) v in = 50mv p-p , freq = 2.7gbps random jitter vs. input amplitude max3747/max3747a toc09 differential input amplitude (mv p-p ) random jitter (ps rms ) 1000 100 10 1 2 3 4 5 0 1 10,000 3.2gbps bit-error ratio vs. input voltage max3747/max3747a toc10 differential input amplitude (mv p-p ) bit-error ratio (10 -12 ) 9 8 6 7 2 3 4 5 1 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 11,000 12,000 13,000 1 010 maxim max3747 micrel sy88993v t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.)
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) deterministic jitter vs. input amplitude max3747/max3747a toc11 differential input amplitude (mv p-p ) deterministic jitter (ps p-p ) 1000 100 10 5 10 15 20 25 0 1 10,000 3.2gbps, k28.5 pattern 0 25 20 15 10 5 30 35 40 -40 -20 -10 -30 0 10 20 30 40 50 60 70 80 deterministic jitter vs. temperature max3747/max3747a toc12 temperature ( c) deterministic jitter (ps) freq = 3.2gbps pattern = k28.5 v in = 500mv p-p v in = 5mv p-p assert/deassert vs. v th max3747/max3747a toc13 v th (v) assert/deassert (mv p-p ) -1.2 10 20 30 40 50 60 70 90 110 80 100 120 0 -1.4 0 -0.2 -0.4 -0.6 -0.8 -1.0 v th (v) = voltage at pin 5 (v) with respect to v cc deassert assert 5 20 15 10 25 30 40 35 -40 -20 -10 -30 0 10 20 30 40 50 60 70 80 assert/deassert vs. temperature max3747/max3747a toc14 temperature ( c) assert/deassert (mv) v th = -1.1v, freq = 2.7gbps pattern = prbs 2 23 - 1 assert deassert output return vs. frequency (sdd22) (input signal level = -60dbm) max3747/max3747a toc15 frequency (mhz) sdd22 (db) 1000 -20 -10 0 10 20 30 -30 100 10,000 input return vs. frequency (sdd11) (input signal level = -60dbm) max3747/max3747a toc16 frequency (mhz) sdd11 (db) 1000 -20 -10 0 10 20 30 -30 100 10,000
detailed description the limiting amplifiers consist of a multistage amplifier, offset-correction circuitry, an output buffer, and loss-of- signal detect circuitry (see the functional diagram ). input stage the input stage is shown in figure 3. it provides 50 ? termination to v ref for each input signal, in+ and in-. the max3747/max3747a should be ac-coupled. multistage amplifier the high-bandwidth multistage amplifier provides approximately 57db of gain for the max3747 and 61db of gain for the max3747a. offset correction loop the max3747/max3747a are susceptible to dc offsets in the signal path because they have high gain. in com- munication systems using nrz data with a 50% duty cycle, pulse-width distortion present in the signal or gen- erated in the transimpedance amplifier appears as an input offset and is reduced by the offset correction loop. the offset correction loop sets a low-frequency cutoff of 3.2khz. max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers _______________________________________________________________________________________ 7 pin description max3747/ max3747a micrel sy8893v pin name name function 1 disable en disable function pin. the data outputs are held static when this pin is asserted high, transistor-to-transistor logic (ttl). 2 in+ din noninverted input signal, cml 3 in- din inverted input signal, cml 4v ref v ref reference voltage for los threshold setting 5t h loslvl loss-of-signal level set. a voltage on this pin created by a two-resistor divider sets the threshold level. connect one resistor from this pin to v cc and another from this pin to v ref (see figure 5). 6 gnd gnd ground 7 los los loss-of-signal, open collector. los is high when the level of the input signal drops below the preset threshold set by the th input. los is deasserted low when the signal level is above the threshold. 8 out- dout inverted data output, cml 9 out+ dout noninverted data output, cml 10 v cc v cc positive power supply max3747 max3747a 50 ? 50 ? v ref v cc esd structures figure 3. cml input stage
max3747/max3747a cml output buffer the cml outputs of the max3747/max3747a limiting amplifiers provide high tolerance to impedance mis- matches and inductive connectors. the output current is approximately 10ma for the max3747 and 16ma for the max3747a. connecting the disable pin to v cc disables the output. if the los pin is connected to the disable pin, the outputs out+ and out- are at a stat- ic voltage (squelch) whenever the input signal level drops below the los threshold. the output buffer can be ac- or dc-coupled to the load (figure 4). the max3747 output is 500mv p-p and the max3747a output is 800mv p-p . 155mbps to 3.2gbps, low-power sfp limiting amplifiers 8 _______________________________________________________________________________________ max3747 max3747a 50 ? 50 ? digital offset correction v ref signal detect 50 ? 50 ? in+ in- v ref v ref th los v cc v cc out+ disable out- r 1 r 1 + r 2 5k ? r 2 functional diagram 50 ? 50 ? v cc out+ out- disable disable q4 q2 q1 q3 disable data esd structures figure 4. cml output buffer
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers _______________________________________________________________________________________ 9 loss-of-signal indicator the max3747/max3747a are equipped with los cir- cuitry that indicates when the input signal is below a pro- grammable threshold, set by a voltage on the th pin (see the typical operating characteristics ). the voltage on the th pin is set by two resistors, one connecting from the th pin to v cc and the other connecting from th to v ref (figure 5). an rms power detector compares the input signal amplitude with this threshold and feeds the signal-detect information to the los output, which is open collector. to prevent los chatter in the region of the programmed threshold, approximately 2db of hys- teresis is built into the los assert/deassert function. once asserted, los is not deasserted until the input amplitude rises to the required level. figure 6 shows the los output circuit. applications information program the los assert threshold program the los assert threshold according to figure 5. the combination of r1 and r2 should be greater than or equal to 5k ? , see the assert/deassert vs. v th graph in the typical operating characteristics . select the coupling capacitor when ac-coupling is desired, coupling capacitors c in and c out should be selected to minimize the receiv- er? deterministic jitter. jitter is decreased as the input low-frequency cutoff (f in ) is decreased: f in = 1 / [2 (50)(c in )] for all applications, the recommended value for c in and c out is 0.1?, which provides f in equal to 32khz. refer to application note hfan-1.1: choosing ac-coupling capacitors on the maxim website (www.maxim-ic.com) . emi performance the max3747/max3747a have been designed for bet- ter emi performance. to help reduce emi, special care has been taken to produce symmetrical signal outputs. chip information transistor count: 443 process: sige bipolar th v ref r2 r1 v cc v th = (r1 x (v ref - v cc )) / (r2 + r1) v th is v cc referenced r1 + r2 5k ? figure 5. max3747/max3747a los threshold circuit esd structure v cc los figure 6. max3747/max3747a los output circuit 1 2 3 4 5 10 9 8 7 6 v cc out+ out- los v ref in- in+ disable max3747 max3747a max top view gnd th pin configuration
max3747/max3747a 155mbps to 3.2gbps, low-power sfp limiting amplifiers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 00.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1
|
